Sun leaks presentation of upcoming 6-core Xeon CPU

Soo according to The Register Intel has a 6-core Xeon processor(Dunnington) based on the 45nm Penryn architecture coming out in H2 of 2008. The processor will allow each core to share 3MB of L2 Cache with a shared 16MB L3 cache on a 1066MHz Front Side Bus. This chip is supposed to be pin compatible with the Tigerton processors.

My biggest complaint is why would they release this new “state of the art” processor with only a 1066MHz bus? Modern processors(including the Xeon 53xx series) are at 1333MHz with a very select few at the 1600MHz margin. I think this may limit the full potential of these processors, as we already seen such a hit with the Q6600 CPU on a 1066MHz bus.  The only thing I can think of is that this architecture will not be mature enough to run higher bus speeds until the 32nm Nehalem revisions come out in late 2009-early 2010.